This invention relates to a charge coupled device and, more particularly, to a charge coupled device having a miniature charge accumulating layer and a process for fabricating the charge coupled device.
The charge coupled device has found a wide variety of application such as, for example, an image sensor. The charge coupled device used in the image sensor is categorized in a frame-transfer type, and has the structure shown in FIGS. 1A and 1B. The prior art frame-transfer type charge coupled device is fabricated on an n-type semiconductor substrate 1, and a p-type well 11 is formed in a surface portion of the n-type semiconductor substrate 1. P-type isolating regions 2 are spaced from each other in the p-type well 11, and n-type charge accumulating layer 3 is formed between the p-type isolating regions 2. The isolating regions 2 and the n-type charge accumulating layer 3 are covered with an insulating layer 4, and transfer electrodes 5 are patterned on the insulating layer 4 along the charge accumulating layer 3.
A driving pulse signal is selectively applied to the transfer electrodes 5. Then, potential wells are sequentially created in the charge accumulating layer 3 under the transfer electrodes 5, and charge packets are conveyed from the potential wells to the next potential wells. Signal charge forms each charge packet, and is representative of a piece of visual image. A part of the charge accumulating layer for creating a potential well and associated transfer electrode or electrodes 5 are hereinbelow referred to as xe2x80x9cunit cellxe2x80x9d which is a pixel of the frame-transfer type charge coupled device image sensor, also.
Though not shown in FIGS. 1A and 1B, a certain voltage is applied to the n-type substrate 1, and excess signal charge is discharged through the p-type well 11 to the n-type substrate 1. Thus, the adjacent potential wells are prevented from the excess charge. While the charge packets are being conveyed along the charge accumulating layer 3, the p-n junction between the n-type semiconductor substrate 1 and the p-type well 11 is reversely biased, and the p-type well 11 is electrically isolated from the n-type semiconductor substrate 1. When a pulse signal is applied to the n-type semiconductor substrate 1, the p-n junction is much stronger biased in reverse than ever, and the signal charge is discharged to the n-type semiconductor substrate 1. This phenomenon is called as a substrate shutter or an electronic shutter, and the exposure is controlled with the substrate shutter.
Users request the manufacturer to reduce the price of the image sensor. In order to reduce the production cost, the manufacturer scales down the image sensor and, accordingly, the charge coupled device. Another request for the manufacturer is a fine visual image on a screen, and the manufacturer increases the photo-electric converting elements per unit area. This means that the unit cell is miniaturized as well as the photo-electric converting element. Thus, the common concept for both approaches is miniaturization.
Research and development efforts have been made for a miniature unit cell, and it is found that the p-type well is not required for the unit cell. This means that the charge accumulating layer 3, the isolating regions 2 the insulating layer 4 and the transfer electrodes 5 form in combination a charge coupled device as shown in FIGS. 2A and 2B (see xe2x80x9cDesign Options for xc2xcxe2x80x3-FTCCD Pixelsxe2x80x9d, J. T. Bosiers et. al., Proceedings of 1995 IEEE Workshop on Charge- Coupled Devices and Advanced Image Sensors, April, 1995). The prior art charge coupled device without the p-type well is simpler than the standard charge coupled device, and the production cost is reduced. However, the manufacturer encounters the following problems in the miniaturized charge coupled device. First, the isolating regions 2 increase influences on the charge accumulating layer 3, and the designer can not analyze the miniature unit cell as a one-dimensional model in the direction of the depth of the charge accumulating layer 3. Two-dimensional analysis is required for the miniature unit cell. The phenomenon which the designer experiences in the design work for the miniature unit cell is hereinbelow referred to as xe2x80x9ctwo-dimensional effectxe2x80x9d.
In this situation, when the manufacturer designs the charge accumulating layer 3, the amount of actually accumulated signal charge is less than the amount of accumulated signal charge predicted on the basis of the ratio of areas. On the other hand, when the manufacturer designs the substrate shutter, the substrate shutter requires the pulse signal with a higher pulse height for discharging the signal charge to the substrate, because the pulse signal is expected to deplete the isolating regions 2 increased at the ratio of areas as well as the charge accumulating layer 3. If the dopant concentration of the charge accumulating layer 3 is increased, the amount of accumulated signal charge is increased. However, the substrate shutter requires a higher pulse height due to the charge accumulating layer 3 increased in the dopant concentration. The pulse height may exceed the maximum voltage level for portable electronic goods. Moreover, the higher pulse height is causative of increase of the electric power consumption. Thus, there is a trade-off between the increase of the amount of accumulated signal charge and the decrease of the pulse height of the pulse signal.
It is therefore an important object of the present invention to provide a charge coupled device, which has a unit cell increased in the amount of signal charge without sacrifice of the pulse height of a pulse signal used for a substrate shutter.
It is also an important object of the present invention to provide a process for fabricating the charge coupled device.
The present inventors contemplated the problems inherent in the prior art charge coupled device, and found that the dopant impurity concentration was different between a central region of a charge accumulating layer and a peripheral region thereof due to the diffusion of the dopant impurity. The peripheral region was relatively low in the dopant impurity concentration, and was liable to be depleted around the p-n junctions between the charge accumulating layer and the isolating regions. This resulted in that the peripheral region merely accumulated a small amount of signal charge. The two-dimensional effect was derived from the lightly-doped peripheral region.
The present inventors simulated the amount of accumulated charge per unit area for miniature charge accumulating layers, and plotted the amount of accumulated charge per unit area in FIG. 3. The present inventors concluded that the two-dimensional effect became serious in the charge coupled device with the charge accumulating layer equal in width to or less than 5 microns.
Subsequently, the present inventors considered how to restrict the two-dimensional effect. As described hereinbefore, the non-uniform dopant concentration was the origin of the two-dimensional effect. The present inventors made the charge accumulating layer higher in dopant impurity concentration in the peripheral region and lower in the central region. The higher the dopant impurity concentration, the more the amount of accumulated charge. The depletion layer extending from the p-n junction was relatively thin in the heavily-doped peripheral region. An approach to the heavily-doped peripheral region was formed by using a counter doping in the central region, which had been already heavily doped. An impurity region opposite in conductivity type to the central region was formed through the counter doping, and a p-n junction took place between the impurity region and the central region. The p-n junction was conducive to the increase of the amount of accumulated charge.
The reason for the high pulse height was that the electric lines of force were converged for depleting the heavily-doped isolating region as well as the charge accumulating layer. The present inventors considered that a protection for the isolating regions against the electric lines of force was effective against the increase of the pulse height. Otherwise, the electric lines of force had to be converged for depleting the charge accumulating layer before the isolating regions. The present inventors noticed that the p-n junction formed through the counter doping was available for the convergence of the electric lines of force. However, it is important to space the impurity region formed through the counter-doping from the isolating regions. Because the impurity region held in contact with the isolating regions merely prolonged the p-n junctions of the isolating regions. Thus, the impurity region formed through the counter doping was locally formed under the charge accumulating layer.
To accomplish the object, the present invention proposes to form an impurity region opposite in conductivity type to a charge accumulating layer locally under the charge accumulating layer.
In accordance with one aspect of the present invention, there is provided a charge coupled device fabricated on a semiconductor substrate of a first conductivity type isolating regions having a second conductivity type opposite to the first conductivity type and spaced from each other in a surface portion of the semiconductor substrate, a charge accumulating layer of the first conductivity type formed in the surface portion between the isolating regions, an insulating layer formed on the isolating regions and the charge accumulating layer, transfer electrodes formed on the insulating layer along the charge accumulating layer and a local impurity region of the second conductivity type formed in the semiconductor substrate, projecting into a central region of the charge accumulating layer for forming a p-n junction and spaced from the isolating regions.
In accordance with another aspect of the present invention, there is provided a process for fabricating a charge coupled device comprising the steps of a) preparing a semiconductor substrate of a first conductivity type covered with an insulating layer, b) introducing a first dopant impurity into a surface portion of the semiconductor substrate for forming a charge accumulating layer of the first conductivity type, c) introducing a second dopant impurity purity into surface portions of the semiconductor substrate on both sides of the surface portion for forming isolating regions of a second conductivity type opposite to the first conductivity type, d) introducing a third dopant impurity into a region of the semiconductor substrate for forming a local impurity region of the second conductivity type projecting into a central region of the charge accumulating layer and spaced from the isolating regions and e) forming transfer electrodes over the charge accumulating layer.